低压功率pmosfet的漏阻电流权衡

Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI:10.1109/ISPSD.1995.515046

M. Darwish, R.K. Williams, M. S. Shekar, T. Chan

{"title":"低压功率pmosfet的漏阻电流权衡","authors":"M. Darwish, R.K. Williams, M. S. Shekar, T. Chan","doi":"10.1109/ISPSD.1995.515046","DOIUrl":null,"url":null,"abstract":"The trade-offs that impact minimizing on-resistance while maintaining an acceptable level of leakage current in very low on-resistance buried p-channel MOSFETs are investigated. Gate induced drain leakage (GIDL) current in power PMOSFETs is studied both experimentally and by using numerical simulations. The effect of several carrier generation mechanisms such as band-to-band tunneling, avalanche multiplication and thermal generation on leakage current are also discussed.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On resistance-leakage current trade-off in low-voltage power PMOSFETs\",\"authors\":\"M. Darwish, R.K. Williams, M. S. Shekar, T. Chan\",\"doi\":\"10.1109/ISPSD.1995.515046\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The trade-offs that impact minimizing on-resistance while maintaining an acceptable level of leakage current in very low on-resistance buried p-channel MOSFETs are investigated. Gate induced drain leakage (GIDL) current in power PMOSFETs is studied both experimentally and by using numerical simulations. The effect of several carrier generation mechanisms such as band-to-band tunneling, avalanche multiplication and thermal generation on leakage current are also discussed.\",\"PeriodicalId\":200109,\"journal\":{\"name\":\"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1995.515046\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1995.515046","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

在极低导通电阻的埋置p沟道mosfet中，如何在保持可接受的漏电流水平的同时最小化导通电阻?对功率pmosfet的栅极感应漏极电流进行了实验研究和数值模拟。讨论了带间隧穿、雪崩倍增和热产生等载流子产生机制对漏电流的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

On resistance-leakage current trade-off in low-voltage power PMOSFETs

The trade-offs that impact minimizing on-resistance while maintaining an acceptable level of leakage current in very low on-resistance buried p-channel MOSFETs are investigated. Gate induced drain leakage (GIDL) current in power PMOSFETs is studied both experimentally and by using numerical simulations. The effect of several carrier generation mechanisms such as band-to-band tunneling, avalanche multiplication and thermal generation on leakage current are also discussed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95

自引率

0.00%

发文量