Equations for selection of cost-efficient interconnection designs

Attempts to extend the utility of the price/density diagram for interconnection substrates by deriving a number of theoretical relationships for analyzing the costs of interconnections in a more general way, and a number of equations are given which relate the cost of interconnections to their density. It is shown that there exists a set of 'saddle-shaped' cost/density relationships for each technology selected for the manufacture of the interconnecting substrates. Practical application of these equations is illustrated by empirical results confirming their applicability in a realistic design environment. A method for calculating the effects of yields of a selected manufacturing processes on the interconnection costs is shown. It is demonstrated that this method can be extended to provide information about the economically optimal design of conductor widths on interconnecting substrates. The authors present an example showing the application of the derived equations to the problem of packaging a CPU with 6*10/sup 6/ gates, using the most efficient interconnection solution for the entire system, including chips, MCMs (multichip modules), and motherboards.<>