下填土力学性能对倒装芯片局部变形和残余应力的影响

K. Nakahira, Yuki Sato, H. Kishi, K. Suzuki, H. Miura
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引用次数: 1

摘要

由于3D集成中堆叠硅芯片的厚度被减薄到100µm以下,芯片的局部热变形急剧增加,这是因为减薄后芯片的抗弯刚度降低了。由于金属凸点的周期性排列,堆积芯片中出现明显的周期性热变形,从而产生热残余应力分布,降低了产品的可靠性。本文在三维有限元分析的基础上,利用应变传感器芯片和干涉显微镜对硅片局部变形和残余应力进行了测量,定量地讨论了硅片局部变形的主要结构因素。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effect of the mechanical properties of underfill on the local deformation and residual stress in a chip mounted by area-arrayed flip chip structures
Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 µm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appear in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local deformation of a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local deformation and residual stress in a chip using strain sensor chips and interference microscopy.
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