基于90nm及以上CMOS技术节点的PMOS超浅结形成表面工程模拟

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI:10.1109/SISPAD.2003.1233660

J. Bonnouvrier, D. Lenoble, E. Robilliart, T. Schwartzmann, H. Jaouen

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引用次数: 0

摘要

由于最先进的CMOS器件中的结越来越薄，因此硅表面对掺杂物扩散的影响变得越来越大。本文在实验数据的基础上，提出了一种考虑表面效应的标定方法。采用一种简单的插页重组模型对SIMS剖面进行了精确拟合;通过TCAD ID仿真可以很好地再现和验证POED现象。然后，通过二维TCAD仿真，量化了POED对PMOS性能的影响。

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Simulation of surface engineering for ultra shallow junction formation of PMOS for the 90nm CMOS technology node and beyond

Since the junctions in the most advanced CMOS devices are thinner and thinner, the influence of the surface of silicon is thus becoming significant on dopant diffusion. In this paper, based on experimental data, a methodology for calibration is proposed, taking this effect of surface into account. SIMS profiles are accurately fitted by simulation using a simple model of recombination of interstitials; the phenomenon of POED is well reproduced and validated by TCAD ID simulations. Then, the impact of POED on the PMOS performances is quantified by anticipation with 2D TCAD simulations.

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International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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