利用优化的Si Cap和高k金属栅极堆叠,增强SiGe沟道pmosfet的可加性迁移率和降低失态电流

Jungwoo Oh, P. Majhi, R. Jammy, R. Joe, A. Dip, T. Sugawara, Y. Akasaka, T. Kaitsuka, T. Arikado, M. Tomoyasu
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引用次数: 10

摘要

我们已经在选择性生长在Si(100)衬底上的高质量外延SiGe薄膜上展示了高迁移率的pmosfet。在SiGe沟道上加工硅帽后,HfSiO2高k栅极电介质表现出低C-V磁滞(≪10 mV)、界面阱密度(7.5×1010)和栅极漏电流(EOT为13.4Å时为~ 10−2A/cm2),可与硅沟道上的栅极堆相媲美。SiGe通道(60%)所提供的固有迁移率增强通过Si帽(40%)工艺进一步增加,从而使Si通道的组合增强了100%。Si帽工艺还通过改善通道的栅极控制,缓解了SiGe通道的低势垒问题,这是导致小带隙能量SiGe pmosfet的高过态电流的主要原因。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si Cap and high-k metal gate stacks
We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO2 high-k gate dielectrics exhibited low C-V hysteresis (≪10 mV), interface trap density (7.5×1010), and gate leakage current (∼10−2A/cm2 at an EOT of 13.4Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of SiGe channels, which are major causes of the high off-state current of small bandgap energy SiGe pMOSFETs, by improving gate control over the channel.
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