采用可变费米势场板的新型高压LDMOS,可实现最佳的开关FOM和可靠性权衡

Yun Shi, Santosh K. Sharma, M. Zierak, R. Phelps, D. Cook, T. Letavic
{"title":"采用可变费米势场板的新型高压LDMOS,可实现最佳的开关FOM和可靠性权衡","authors":"Yun Shi, Santosh K. Sharma, M. Zierak, R. Phelps, D. Cook, T. Letavic","doi":"10.1109/ISPSD.2013.6694446","DOIUrl":null,"url":null,"abstract":"In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp*Qgg) and a robust Id, lin shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Novel high voltage LDMOS using a variable fermi-potential field plate for best switching FOM and reliability tradeoff\",\"authors\":\"Yun Shi, Santosh K. Sharma, M. Zierak, R. Phelps, D. Cook, T. Letavic\",\"doi\":\"10.1109/ISPSD.2013.6694446\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp*Qgg) and a robust Id, lin shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.\",\"PeriodicalId\":175520,\"journal\":{\"name\":\"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2013.6694446\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2013.6694446","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

在本文中,我们讨论了一个集成的高压LDMOS在特定导通电阻(Ron, sp)、栅极电荷(Cgg)、准饱和和可靠性特性之间的基本设计权衡。提出了一种新颖的栅极图案设计,并在120v额定NLDMOS中实现。优化设计特性证明了30%的改进开关FOM (Ron, sp*Qgg)和一个稳健的Id, lin移位通过15年的寿命规格。新的设计技术被证明可以显著改善高压LDMOS设计的权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Novel high voltage LDMOS using a variable fermi-potential field plate for best switching FOM and reliability tradeoff
In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp*Qgg) and a robust Id, lin shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信