Yuji Harada, K. Yoshikawa, N. Miura, M. Nagata, Akitaka Murata, Syuji Agatsuma, K. Ichikawa
{"title":"小型逆变器链的功率噪声测量","authors":"Yuji Harada, K. Yoshikawa, N. Miura, M. Nagata, Akitaka Murata, Syuji Agatsuma, K. Ichikawa","doi":"10.1109/IMFEDK.2013.6602259","DOIUrl":null,"url":null,"abstract":"This paper presents the measurements of power noise (Vdd noise) waveforms of a 5-stage inverter chain, using on-chip noise monitor circuits (OCM). The fine resolution of 0.4 mV in voltage and 12.5 ps in timing are realized. The undesired voltage variation by signal buffers in I/O cells is carefully eliminated by three means; (i) isolation of power domains, (ii) subtraction of background noise waveforms, and (iii) averaging iteratively captured waveforms.","PeriodicalId":434595,"journal":{"name":"2013 IEEE International Meeting for Future of Electron Devices, Kansai","volume":"184 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Power-noise measurements of small-scale inverter chains\",\"authors\":\"Yuji Harada, K. Yoshikawa, N. Miura, M. Nagata, Akitaka Murata, Syuji Agatsuma, K. Ichikawa\",\"doi\":\"10.1109/IMFEDK.2013.6602259\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the measurements of power noise (Vdd noise) waveforms of a 5-stage inverter chain, using on-chip noise monitor circuits (OCM). The fine resolution of 0.4 mV in voltage and 12.5 ps in timing are realized. The undesired voltage variation by signal buffers in I/O cells is carefully eliminated by three means; (i) isolation of power domains, (ii) subtraction of background noise waveforms, and (iii) averaging iteratively captured waveforms.\",\"PeriodicalId\":434595,\"journal\":{\"name\":\"2013 IEEE International Meeting for Future of Electron Devices, Kansai\",\"volume\":\"184 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Meeting for Future of Electron Devices, Kansai\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMFEDK.2013.6602259\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Meeting for Future of Electron Devices, Kansai","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMFEDK.2013.6602259","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Power-noise measurements of small-scale inverter chains
This paper presents the measurements of power noise (Vdd noise) waveforms of a 5-stage inverter chain, using on-chip noise monitor circuits (OCM). The fine resolution of 0.4 mV in voltage and 12.5 ps in timing are realized. The undesired voltage variation by signal buffers in I/O cells is carefully eliminated by three means; (i) isolation of power domains, (ii) subtraction of background noise waveforms, and (iii) averaging iteratively captured waveforms.