{"title":"32纳米及以上节点MOSFET的缩放挑战","authors":"Y. Nara","doi":"10.1109/VTSA.2009.5159296","DOIUrl":null,"url":null,"abstract":"Scaling challenges for MOSFET fabrication process with design rule of 32nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with scaled dimensions.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"172 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Scaling challenges of MOSFET for 32nm node and beyond\",\"authors\":\"Y. Nara\",\"doi\":\"10.1109/VTSA.2009.5159296\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Scaling challenges for MOSFET fabrication process with design rule of 32nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with scaled dimensions.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":\"172 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159296\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159296","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scaling challenges of MOSFET for 32nm node and beyond
Scaling challenges for MOSFET fabrication process with design rule of 32nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with scaled dimensions.
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