在PCB上跟踪错配余量多少才够?

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-10-01 DOI:10.1109/EPEPS.2015.7347154

Cong Gao, Pravin Patel

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引用次数: 0

摘要

对于高速互连设计，由于走线错配引起的走线串扰可能高达连接器和过孔。这样的相声一定要管理好。本文从错配余量的角度对迹串扰进行了参数化研究，为实际系统设计提供了指导。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Trace mis-registration margin on PCB how much is enough?

For high speed interconnect design, trace crosstalk due to trace mis-registration can be as high as connector and vias. One should make sure such crosstalk is well managed. This paper presents the parametric study on trace crosstalk with respect to the mis-registration margin and provides some guidelines in practical system designs.

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2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

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