Parylene N as a dielectric material for through silicon vias

This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200 mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate.