{"title":"利用综合建模方法预测系统级ESD稳健性","authors":"C. Russ, Michael Ammer, K. Esmark","doi":"10.23919/EOS/ESD.2018.8509746","DOIUrl":null,"url":null,"abstract":"The system level ESD robustness of ICs is simulated including all external components. An electro-thermal model is calibrated to power profiles of IC failures. Results provide great confidence for prediction of the joint effectiveness of board- or chip-level protection in reaction to changing system requirements or to different ESD guns.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Predicting System Level ESD Robustness Using a Comprehensive Modelling Approach\",\"authors\":\"C. Russ, Michael Ammer, K. Esmark\",\"doi\":\"10.23919/EOS/ESD.2018.8509746\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The system level ESD robustness of ICs is simulated including all external components. An electro-thermal model is calibrated to power profiles of IC failures. Results provide great confidence for prediction of the joint effectiveness of board- or chip-level protection in reaction to changing system requirements or to different ESD guns.\",\"PeriodicalId\":328499,\"journal\":{\"name\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/EOS/ESD.2018.8509746\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EOS/ESD.2018.8509746","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Predicting System Level ESD Robustness Using a Comprehensive Modelling Approach
The system level ESD robustness of ICs is simulated including all external components. An electro-thermal model is calibrated to power profiles of IC failures. Results provide great confidence for prediction of the joint effectiveness of board- or chip-level protection in reaction to changing system requirements or to different ESD guns.