SRAM芯单元中电阻性桥接缺陷的影响

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI:10.1109/DELTA.2010.31

R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine

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引用次数: 7

摘要

在本文中，我们提出了一项研究的影响电阻桥接缺陷在SRAM核心单元。电阻桥的位置的选择考虑了实际的工业核心单元布局。我们进行了大量的模拟，改变了缺陷的电阻值，电源电压，频率和温度。实验结果表明，故障不仅发生在有缺陷的核心细胞内，而且发生在存储阵列的其他核心细胞(无缺陷)中。发现了静态和动态断层，单细胞和双细胞断层。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of Resistive-Bridging Defects in SRAM Core-Cell

In this paper, we present a study on the effects of resistive-bridging defects in the SRAM core-cell. The position of the resistive-bridges has been chosen taking in account an actual industrial core-cell layout. We have performed an extensive number of simulations, varying the resistance value of the defects, supply voltage, frequency and temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array. Static and dynamic faults, single-cell and double-cells faults have been found.

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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications

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