非共线PNPN结构的锁存模型

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2018-09-01 DOI:10.23919/EOS/ESD.2018.8509739

Collin Reiman, N. Jack, E. Rosenbaum

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引用次数: 2

摘要

非共线PNPN器件中锁存的可扩展I-V模型改编自以前的共线SCR器件模型。该模型应用于14nm FinFET测试结构。在电路仿真中，该模型捕获了关键锁存指标(如保持电压和触发电压)的布局缩放趋势。TCAD模拟用于获得对非共线PNPN器件行为的物理洞察。

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Latch-up Model of Non-collinear PNPN Structures

A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to 14-nm FinFET test structures. Layout scaling trends for key latch-up metrics, such as holding and trigger voltage, are captured by the model in circuit simulation. TCAD simulation is used to gain physical insight into the behavior of non-collinear PNPN devices.

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来源期刊

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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