100Gbit/s SiGe时钟和数据恢复

2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI:10.1109/BCTM.2013.6798175

Q. Beraud-Sudreau, J. Bégueret, O. Mazouffre, M. Pignol, L. Baguena, C. Neveu, Y. Deval, T. Taris

{"title":"100Gbit/s SiGe时钟和数据恢复","authors":"Q. Beraud-Sudreau, J. Bégueret, O. Mazouffre, M. Pignol, L. Baguena, C. Neveu, Y. Deval, T. Taris","doi":"10.1109/BCTM.2013.6798175","DOIUrl":null,"url":null,"abstract":"Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"413 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"100Gbit/s SiGe Clock and Data Recovery\",\"authors\":\"Q. Beraud-Sudreau, J. Bégueret, O. Mazouffre, M. Pignol, L. Baguena, C. Neveu, Y. Deval, T. Taris\",\"doi\":\"10.1109/BCTM.2013.6798175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.\",\"PeriodicalId\":272941,\"journal\":{\"name\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"volume\":\"413 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCTM.2013.6798175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2013.6798175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

时钟和数据恢复(Clock and data recovery, CDR)是串行数据接收器的第一个逻辑块，后者的性能取决于CDR的性能。提出了一种采用130 nm BiCMOS SiGe工艺设计的100gbit /s CDR。CDR使用注入锁定振荡器(ILO)和反馈环路来锁定数据和时钟的频率和相位。2.3 V供电时，功耗为1.4 W。

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100Gbit/s SiGe Clock and Data Recovery

Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.

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2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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