{"title":"倒装片再分配层电特性及单点登录噪声仿真","authors":"Zhonghua Wu, O. Siguenza","doi":"10.1109/EPEP.1997.634052","DOIUrl":null,"url":null,"abstract":"Electrical characterization of flip-chip redistribution layer and detailed study of the associated ohmic drop, simultaneous switching output (SSO) noise and crosstalk are presented. Noise margins are analyzed and design rules are generated based on the simulation.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Flip-chip redistribution layer electrical characterization and SSO noise simulation\",\"authors\":\"Zhonghua Wu, O. Siguenza\",\"doi\":\"10.1109/EPEP.1997.634052\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electrical characterization of flip-chip redistribution layer and detailed study of the associated ohmic drop, simultaneous switching output (SSO) noise and crosstalk are presented. Noise margins are analyzed and design rules are generated based on the simulation.\",\"PeriodicalId\":220951,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.1997.634052\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1997.634052","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Flip-chip redistribution layer electrical characterization and SSO noise simulation
Electrical characterization of flip-chip redistribution layer and detailed study of the associated ohmic drop, simultaneous switching output (SSO) noise and crosstalk are presented. Noise margins are analyzed and design rules are generated based on the simulation.
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