C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy
{"title":"高可靠性和高性能0.35 μ m栅极倒转TFT，用于使用自对准LDD结构的16 Mbit SRAM应用","authors":"C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy","doi":"10.1109/IEDM.1992.307484","DOIUrl":null,"url":null,"abstract":"A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"83 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"High reliability and high performance 0.35 mu m gate-inverted TFT's for 16 Mbit SRAM applications using self-aligned LDD structures\",\"authors\":\"C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy\",\"doi\":\"10.1109/IEDM.1992.307484\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<<ETX>>\",\"PeriodicalId\":287098,\"journal\":{\"name\":\"1992 International Technical Digest on Electron Devices Meeting\",\"volume\":\"83 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 International Technical Digest on Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1992.307484\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307484","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High reliability and high performance 0.35 mu m gate-inverted TFT's for 16 Mbit SRAM applications using self-aligned LDD structures
A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<>
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