用于ESD测试的TLP中击穿脉冲数的仿真

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI:10.1109/SISPAD.2003.1233654

K. Matsuzawa, H. Satake, C. Sutou, H. Kawashima

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引用次数: 6

摘要

采用器件仿真的方法，研究了nmosfet栅极绝缘子在传输线脉冲静电放电试验中的击穿特性。采用阳极-空穴注入模型再现了栅极偏压和栅极氧化层厚度随击穿脉冲数变化的实验数据。栅极偏压的极性对击穿特性的依赖可以用栅极电极的耗尽来解释。

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Simulation of number of pulses to breakdown during TLP for ESD testing

The breakdown characteristics of the gate insulator of nMOSFETs during transmission line pulsing for electrostatic discharge testing is evaluated by using device simulations. Experimental data for the gate bias and gate oxide thickness dependences of the number of pulses to breakdown are reproduced by adopting the anode-hole-injection model. The polarity of the gate bias dependence of the breakdown characteristics can be explained by the depletion of the gate electrode.

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来源期刊

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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