模拟开孔缺陷

16th Asian Test Symposium (ATS 2007) Pub Date : 2007-10-08 DOI:10.1109/ATS.2007.72

S. Spinner, Jie Jiang, I. Polian, P. Engelke, B. Becker

{"title":"模拟开孔缺陷","authors":"S. Spinner, Jie Jiang, I. Polian, P. Engelke, B. Becker","doi":"10.1109/ATS.2007.72","DOIUrl":null,"url":null,"abstract":"Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Simulating Open-Via Defects\",\"authors\":\"S. Spinner, Jie Jiang, I. Polian, P. Engelke, B. Becker\",\"doi\":\"10.1109/ATS.2007.72\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.\",\"PeriodicalId\":289969,\"journal\":{\"name\":\"16th Asian Test Symposium (ATS 2007)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"16th Asian Test Symposium (ATS 2007)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2007.72\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th Asian Test Symposium (ATS 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2007.72","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 14

摘要

开孔缺陷是纳米制造过程中主要的系统性失效机制。我们提出了一个模拟开孔缺陷的流程。从布局和工艺数据中提取电气参数，并以一种能够在栅极级进行有效仿真的方式表示。该仿真器考虑了通孔缺陷引起的振荡，并量化了其对缺陷覆盖率的影响。该流程既可用于制造试验，也可用于缺陷诊断。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Simulating Open-Via Defects

Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

16th Asian Test Symposium (ATS 2007)

自引率

0.00%

发文量