缩放dram中I/ o引脚锁存的TCAD诊断

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095) Pub Date : 1996-09-02 DOI:10.1109/SISPAD.1996.865317

K. Tsuneno, H. Sato, S. Narui, H. Masuda

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引用次数: 0

摘要

只提供摘要形式。本文介绍了一种浅井CMOS DRAM I/ o引脚闭锁失效的TCAD分析方法。在JEDEC标准过流应力的闭锁测试中，0.35 /spl mu/m的DRAM I/ o引脚表现出明显的退化。对故障进行了TCAD诊断，重新阐明了保护带(N/sup +/)层的偏置效应和与布局相关的闭锁机制，从而实现了亚/spl μ m CMOS工艺和布局的实用闭锁抗扰设计。为了克服工艺裕度问题，提出了一种用于0.35 /spl mu/m DRAM的简单CMOS工艺。

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TCAD diagnosis of I/O-pin latchup in scaled-DRAM

Summary form only given. This paper describes a TCAD analysis of I/O-pin latchup failure found in a shallow-well CMOS DRAM. The 0.35 /spl mu/m DRAM I/O-pin showed significant degradation in latchup test of JEDEC Standard over-current stress. TCAD diagnosis of the failure was conducted and newly clarified the biasing effect of the guard-band (N/sup +/) layer and the layout-related latchup mechanism, which leads to a practical latchup-immunity design in sub-/spl mu/m CMOS process and layout. To overcome process-margin problem against latchup, a simple CMOS process is proposed for the 0.35 /spl mu/m DRAM.

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来源期刊

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)

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