Localization techniques for finding embedded defects in stacked die package

Driven by the next generation of electronic devices that require progressive miniaturization, stacked die packages have been developed to provide greater functionality in smaller package footprints. This provides a substantial improvement in the electrical performance while enabling continuous extension of the Moore's Law. Nevertheless, high circuit density and high complexity of interconnections have posed a great challenge to failure analysis work. In this paper, the application of lock-in infrared thermography technique coupled with detailed physical deprocessing work in finding embedded defects in stacked memory die packages are broadly discussed.