{"title":"一种集成电容器阵列匹配特性的测试结构","authors":"W. Posch, G. Promitzer, E. Seebacher","doi":"10.1109/ICMTS.2010.5466833","DOIUrl":null,"url":null,"abstract":"A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations σ(δCi / C) and the offsets μ(δCi / C) of units i. Furthermore, the measurement repeatability is determined and an advanced derivation to consider the correlations introduced by the circuit structure and the extraction method is presented. The corresponding test chips were successfully realized in 0.35 um and 0.18 um standard CMOS technologies.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A test structure for integrated capacitor array matching characterization\",\"authors\":\"W. Posch, G. Promitzer, E. Seebacher\",\"doi\":\"10.1109/ICMTS.2010.5466833\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations σ(δCi / C) and the offsets μ(δCi / C) of units i. Furthermore, the measurement repeatability is determined and an advanced derivation to consider the correlations introduced by the circuit structure and the extraction method is presented. The corresponding test chips were successfully realized in 0.35 um and 0.18 um standard CMOS technologies.\",\"PeriodicalId\":153086,\"journal\":{\"name\":\"2010 International Conference on Microelectronic Test Structures (ICMTS)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Microelectronic Test Structures (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2010.5466833\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2010.5466833","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A test structure for integrated capacitor array matching characterization
A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations σ(δCi / C) and the offsets μ(δCi / C) of units i. Furthermore, the measurement repeatability is determined and an advanced derivation to consider the correlations introduced by the circuit structure and the extraction method is presented. The corresponding test chips were successfully realized in 0.35 um and 0.18 um standard CMOS technologies.
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