0.16-μm 30-V/1.8 v BCD技术中HV-LDMOS与LV-CMOS的闭锁路径研究

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2018-09-01 DOI:10.23919/EOS/ESD.2018.8509772

Chia-Tsen Dai, M. Ker, Yeh-Ning Jou, Shao-Chang Huang, Geeng-Lih Lin, Jian-Hsing Lee

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引用次数: 2

摘要

研究了0.16 μm 30 v /1.8 v双极cmos - dmos (BCD)技术中高压PMOS与低压PMOS的锁存路径。从硅片上的实验结果来看，在电流触发闭锁测试中，该路径很容易被诱导进入闭锁状态。因此，应仔细指定相关的布局规则，以避免此类高压-低压跨域锁定问题。

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Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology

The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30-V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.

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2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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