20nm低功耗三栅极多体1T-DRAM单元

Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI:10.1109/VLSI-TSA.2012.6210166

F. Gámiz, N. Rodriguez, S. Cristoloveanu

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引用次数: 1

摘要

新概念的三栅极1T-DRAM单元采用N/P体分隔，实现空穴存储和电子电流的物理分离。空穴浓度控制着n核的部分或全部耗竭。该单元兼容最终缩放，并显示有吸引力的性能(长保留，宽内存窗口，简单的编程，非破坏性读取，非常低功耗的操作)嵌入式系统。

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A 20nm low-power triple-gate multibody 1T-DRAM cell

The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.

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Proceedings of Technical Program of 2012 VLSI Technology, System and Application

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