Solder shape design and thermal stress/strain analysis of flip chip packaging using hybrid method

As the interconnection density of electronic packaging continues to increase, fatigue-induced solder joint failure of surface mounted electronic devices has become a critical reliability theme in electronic packaging. Therefore, prediction of the solder joint shape is a major part of the development of electronic packaging for practical applications. In conventional electronic packaging, the geometrical dimensions of solder balls and solder pads remain the same. The maximum thermally induced stress/strain occurred on top surface of the solder joints located farthest away from the chip center, and may reduce the reliability life of the entire package. In this research, a hybrid method combining analytical and energy based methods is utilized to predict force-balanced heights and geometry profiles of solder balls under various solder volume and pad dimensions as well as their relative location during the reflow process. Next, the ANSYS finite element analysis code is implemented to investigate the stress/strain behavior of solder balls in flip chip packages under temperature cycles. The results reveals that as the flip chip package contains larger solder balls located at corner area underneath the chip, the maximum equivalent plastic strain/stress is evidently reduced and the reliability cycles under thermal loading are enhanced. Furthermore, the results presented in this research can be used as design guidelines for area array interconnections such as CSP, flip chip, wafer level packaging and fine pitch BGA.