gb /s双极lsi的低功耗设计方法

Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI:10.1109/BIPOL.1995.493876

K. Koike, K. Kawai, A. Onozawa, Y. Kobayashi, H. Ichino

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引用次数: 6

摘要

描述了一种低功耗Gbit/s双极标准单元LSI设计方法。它具有性能驱动的布局，高度精确的静态时序分析和基于cad的功耗优化。5.6 k栅极SDH信号处理LSI的工作速率为1.6 Gbit/s，功耗仅为3.9 W。

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Low-power design methodology for Gbit/s bipolar LSIs

A low-power Gbit/s operating bipolar standard cell LSI design methodology is described. It features a performance-driven layout, highly accurate static timing analysis, and CAD-based optimization for power dissipation. A 5.6-k-gate SDH signal-processing LSI operates at 1.6 Gbit/s with only 3.9 W power consumption.

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Proceedings of Bipolar/Bicmos Circuits and Technology Meeting

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