{"title":"PNP双极结构设计为低电压0.6 /spl mu/m互补BiCMOS技术","authors":"M. Belaroussi, B. Djezzar, S. Mekhaldi","doi":"10.1109/HKEDM.1997.642323","DOIUrl":null,"url":null,"abstract":"This paper describes simulation results of a vertical PNP bipolar structure design suitable for low voltage application which can be fabricated in BiCMOS technology. This study is carried out using a mixed two dimensional numerical device/circuit simulation program called CODECS. The simulations show that adding a medium performance PNP transistor, the performance of the complementary BiCMOS over conventional BiCMOS and CMOS were greatly improved as the supply voltage is lowered and the design rules is scaled down to 0.6 /spl mu/m.","PeriodicalId":262767,"journal":{"name":"1997 IEEE Hong Kong Proceedings Electron Devices Meeting","volume":"C-23 9","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"PNP bipolar structure design for low voltage 0.6 /spl mu/m complementary BiCMOS technology\",\"authors\":\"M. Belaroussi, B. Djezzar, S. Mekhaldi\",\"doi\":\"10.1109/HKEDM.1997.642323\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes simulation results of a vertical PNP bipolar structure design suitable for low voltage application which can be fabricated in BiCMOS technology. This study is carried out using a mixed two dimensional numerical device/circuit simulation program called CODECS. The simulations show that adding a medium performance PNP transistor, the performance of the complementary BiCMOS over conventional BiCMOS and CMOS were greatly improved as the supply voltage is lowered and the design rules is scaled down to 0.6 /spl mu/m.\",\"PeriodicalId\":262767,\"journal\":{\"name\":\"1997 IEEE Hong Kong Proceedings Electron Devices Meeting\",\"volume\":\"C-23 9\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-08-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 IEEE Hong Kong Proceedings Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HKEDM.1997.642323\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE Hong Kong Proceedings Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HKEDM.1997.642323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
PNP bipolar structure design for low voltage 0.6 /spl mu/m complementary BiCMOS technology
This paper describes simulation results of a vertical PNP bipolar structure design suitable for low voltage application which can be fabricated in BiCMOS technology. This study is carried out using a mixed two dimensional numerical device/circuit simulation program called CODECS. The simulations show that adding a medium performance PNP transistor, the performance of the complementary BiCMOS over conventional BiCMOS and CMOS were greatly improved as the supply voltage is lowered and the design rules is scaled down to 0.6 /spl mu/m.