The determination of annealing program for NiSi formation

The objective of this research was to form a uniform NiSi layer on MOSFET devices. It has been widely recognized that two-step rapid thermal processing (RTP) is much more effective than one-step RTP in controlling the silicide thickness, and reverse narrow poly line effect. In addition to verifying the number of RTP process steps, soak annealing and spike annealing were intensively investigated to find the most beneficial annealing program. In this paper, we present the progress we made with soak and spike anneals, as well as the effects of implementing them in either RTP1 or RTP2 step in NiSi formation. The results indicate that if a soak anneal was adopted for RTP1 step, the phase transformation is more gentle than a spike anneal, which leads to fewer e-beam inspection defects, better surface roughness, and superior device performance. If a spike anneal was applied as RTP2 step, it would result in much fewer bright voltage contrast (BVC) defects by e-beam inspection on NMOS, compared to a soak anneal. This would suppress the structure defect found in the NMOS NiSi layer, and greatly alleviate the N+/P-well junction leakage degradation issue