用于高压应用的无eos - pnp增强级联NMOSFET结构

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI:10.1109/IRPS.2011.5784506

Shih-Yu Wang, Yao-Wen Chang, Yan-yu Chen, Chieh-Wei He, Guan-Wei Wu, T. Lu, Kuang-Chao Chen, Chih-Yuan Lu

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引用次数: 3

摘要

提出了一种无eos的pnp增强级联NMOSFET结构，用于高压应用。通过控制级联NMOSFET第一栅极的偏置，无EOS控制电路不仅可以在正常高压(HV)工作时提高保持电压，防止EOS损坏的威胁，而且可以在ESD应力下保持较强的ESD鲁棒性。本文通过一个简单的EOS仿真测试，成功地验证了改进后的EOS抗扰度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application

An EOS-free PNP-enhanced cascoded NMOSFET structure for high voltage application is proposed. By controlling the bias of the first gate of cascoded NMOSFET, the EOS-free control circuit can not only raise the holding voltage in normal high voltage (HV) operation to prevent from the threats of EOS damages, but also retain the strong ESD robustness during ESD stress. The improved EOS immunity is successfully verified by a simple EOS-emulating test in this paper.

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2011 International Reliability Physics Symposium

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