A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchi, T. Ogura, T. Matsudai
{"title":"薄SOI上高压功率集成电路的前景","authors":"A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchi, T. Ogura, T. Matsudai","doi":"10.1109/IEDM.1992.307348","DOIUrl":null,"url":null,"abstract":"Silicon on Insulator technology is promising for high voltage power IC applications. The required SOI layer thickness can be reduced if a large portion of the applied voltage is sustained by the bottom insulator layer. Combination of SOI and trenches or LOCOS has merits of simplified device isolation and high device packing density. Thin SOI layer will realize high-speed switching in high voltage devices because of the smaller amount of stored carriers. Substrate bias influences on device characteristics and potentials of SOI technology are discussed.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"39","resultStr":"{\"title\":\"Prospects of high voltage power ICs on thin SOI\",\"authors\":\"A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchi, T. Ogura, T. Matsudai\",\"doi\":\"10.1109/IEDM.1992.307348\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Silicon on Insulator technology is promising for high voltage power IC applications. The required SOI layer thickness can be reduced if a large portion of the applied voltage is sustained by the bottom insulator layer. Combination of SOI and trenches or LOCOS has merits of simplified device isolation and high device packing density. Thin SOI layer will realize high-speed switching in high voltage devices because of the smaller amount of stored carriers. Substrate bias influences on device characteristics and potentials of SOI technology are discussed.<<ETX>>\",\"PeriodicalId\":287098,\"journal\":{\"name\":\"1992 International Technical Digest on Electron Devices Meeting\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"39\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 International Technical Digest on Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1992.307348\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307348","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Silicon on Insulator technology is promising for high voltage power IC applications. The required SOI layer thickness can be reduced if a large portion of the applied voltage is sustained by the bottom insulator layer. Combination of SOI and trenches or LOCOS has merits of simplified device isolation and high device packing density. Thin SOI layer will realize high-speed switching in high voltage devices because of the smaller amount of stored carriers. Substrate bias influences on device characteristics and potentials of SOI technology are discussed.<>
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
