短通道双栅器件阈值电压的物理紧凑模型

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI:10.1109/SISPAD.2003.1233677

Keunwoo Kim, J. Fossum, C. Chuang

{"title":"短通道双栅器件阈值电压的物理紧凑模型","authors":"Keunwoo Kim, J. Fossum, C. Chuang","doi":"10.1109/SISPAD.2003.1233677","DOIUrl":null,"url":null,"abstract":"Compact physics/process-based model for threshold voltage in double-gate devices is presented. Drain-induced barrier lowering and short-channel-induced barrier lowering models for double-gate and bulk-Si devices are derived. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled (L/sub eff/=25 nm) double-gate and bulk-Si devices.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Physical compact model for threshold voltage in short-channel double-gate devices\",\"authors\":\"Keunwoo Kim, J. Fossum, C. Chuang\",\"doi\":\"10.1109/SISPAD.2003.1233677\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Compact physics/process-based model for threshold voltage in double-gate devices is presented. Drain-induced barrier lowering and short-channel-induced barrier lowering models for double-gate and bulk-Si devices are derived. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled (L/sub eff/=25 nm) double-gate and bulk-Si devices.\",\"PeriodicalId\":220325,\"journal\":{\"name\":\"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2003.1233677\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2003.1233677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 22

摘要

提出了双栅器件阈值电压的紧凑物理/工艺模型。推导了双栅和大块硅器件的漏极诱导势垒降低模型和短通道诱导势垒降低模型。通过对尺寸极小(L/sub /=25 nm)双栅和块硅器件的数值模拟，验证了模型的有效性和可预测性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Physical compact model for threshold voltage in short-channel double-gate devices

Compact physics/process-based model for threshold voltage in double-gate devices is presented. Drain-induced barrier lowering and short-channel-induced barrier lowering models for double-gate and bulk-Si devices are derived. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled (L/sub eff/=25 nm) double-gate and bulk-Si devices.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

自引率

0.00%

发文量