{"title":"Rxiensing扫描链用于测试模式解压缩","authors":"R. Dorsch, H. Wunderlich","doi":"10.1109/ETW.2001.946677","DOIUrl":null,"url":null,"abstract":"The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.","PeriodicalId":339694,"journal":{"name":"IEEE European Test Workshop, 2001.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"Rxiensing scan chains for test pattern decompression\",\"authors\":\"R. Dorsch, H. Wunderlich\",\"doi\":\"10.1109/ETW.2001.946677\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.\",\"PeriodicalId\":339694,\"journal\":{\"name\":\"IEEE European Test Workshop, 2001.\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE European Test Workshop, 2001.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ETW.2001.946677\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE European Test Workshop, 2001.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETW.2001.946677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Rxiensing scan chains for test pattern decompression
The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.