先进扇出晶圆级封装(嵌入式晶圆级BGA)的开发

2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) Pub Date : 2012-11-01 DOI:10.1109/IEMT.2012.6521783

Yonggang Jin, J. Teysseyre, A. Liu, G. Goh, S. Yoon

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引用次数: 2

摘要

随着硅技术的降低，芯片与封装界面的间距和衬垫成为重要的因素。这促使互连走向扇形封装，其中封装尺寸大于芯片尺寸，以便提供足够的面积来容纳第二级互连。扇出式WLP有潜力在晶圆节点技术的任何收缩阶段实现任意数量的互连。

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Development of advanced fan-out wafer level package (embedded wafer level BGA)

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.

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2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)

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