Tapered-Shape Channel Engineering for Suppression of Ambipolar Current in TFET

This paper proposes a novel Si-TFET based on a tapered channel structure. The taper-channel design presented in this work provides a higher thickness at the source side than at the drain side, whereas the gate oxide is lesser at the source than at the drain side. The structure is investigated by varying the taper channel length and thickness using Silvaco TCAD simulation. It is found that, by engineering a taper length of 30 nm and thickness of 6 nm, a minimum subthreshold and ambipolar conduction as well as higher ON/OFF current ratio are achieved. The ambipolar current of the optimized structure is approximately $10^{-14}\ \mathrm{A}/\mu\ \mathrm{m}$ compared to 10−10 A/µm regarding the conventional structure. Also, the OFF current is decreased to about $10^{-17}\ \mathrm{A}/\mu\ \mathrm{m}$ with a little drop in ION; however, an increase in the (ON/OFF) current ratio is obtained.