{"title":"多芯片模块互连延迟和串扰的仿真与优化","authors":"M. Nakhla, Q. Zhang","doi":"10.1109/MCMC.1992.201446","DOIUrl":null,"url":null,"abstract":"As signal speeds increase, interconnect effects such as delay, distortion and crosstalk become the dominant factor limiting the overall performance of a multichip module. The authors outline efficient techniques recently developed for addressing three specific aspects of the high-speed interconnect problem, namely, simulation, sensitivity analysis and performance optimization. These techniques accommodate distributed interconnect models represented by lossy coupled transmission lines. Two examples showing the applications of these techniques are included.<<ETX>>","PeriodicalId":202574,"journal":{"name":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Simulation and optimization of interconnect delay and crosstalk in multi-chip modules\",\"authors\":\"M. Nakhla, Q. Zhang\",\"doi\":\"10.1109/MCMC.1992.201446\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As signal speeds increase, interconnect effects such as delay, distortion and crosstalk become the dominant factor limiting the overall performance of a multichip module. The authors outline efficient techniques recently developed for addressing three specific aspects of the high-speed interconnect problem, namely, simulation, sensitivity analysis and performance optimization. These techniques accommodate distributed interconnect models represented by lossy coupled transmission lines. Two examples showing the applications of these techniques are included.<<ETX>>\",\"PeriodicalId\":202574,\"journal\":{\"name\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1992.201446\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1992.201446","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simulation and optimization of interconnect delay and crosstalk in multi-chip modules
As signal speeds increase, interconnect effects such as delay, distortion and crosstalk become the dominant factor limiting the overall performance of a multichip module. The authors outline efficient techniques recently developed for addressing three specific aspects of the high-speed interconnect problem, namely, simulation, sensitivity analysis and performance optimization. These techniques accommodate distributed interconnect models represented by lossy coupled transmission lines. Two examples showing the applications of these techniques are included.<>