Y. Tsukamoto, Koji Obata, Kazuo Matsukawa, K. Sushihara
{"title":"用于物联网传感器的高功率高效和可扩展噪声整形SAR ADC","authors":"Y. Tsukamoto, Koji Obata, Kazuo Matsukawa, K. Sushihara","doi":"10.1109/IMFEDK.2016.7521664","DOIUrl":null,"url":null,"abstract":"A high power efficient and scalable noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. 97.99 dB SNDR and 111.8 dB SFDR for 2 kHz bandwidth with only 37.1 μW power consumption is measured. By increasing sampling frequency, the performance of the ADC is changed to 93.95 dB SNDR and 108.0 SFDR for 20 kHz bandwidth with 493.1 μW power consumption.","PeriodicalId":293371,"journal":{"name":"2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High power efficient and scalable noise-shaping SAR ADC for IoT sensors\",\"authors\":\"Y. Tsukamoto, Koji Obata, Kazuo Matsukawa, K. Sushihara\",\"doi\":\"10.1109/IMFEDK.2016.7521664\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high power efficient and scalable noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. 97.99 dB SNDR and 111.8 dB SFDR for 2 kHz bandwidth with only 37.1 μW power consumption is measured. By increasing sampling frequency, the performance of the ADC is changed to 93.95 dB SNDR and 108.0 SFDR for 20 kHz bandwidth with 493.1 μW power consumption.\",\"PeriodicalId\":293371,\"journal\":{\"name\":\"2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMFEDK.2016.7521664\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMFEDK.2016.7521664","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High power efficient and scalable noise-shaping SAR ADC for IoT sensors
A high power efficient and scalable noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. 97.99 dB SNDR and 111.8 dB SFDR for 2 kHz bandwidth with only 37.1 μW power consumption is measured. By increasing sampling frequency, the performance of the ADC is changed to 93.95 dB SNDR and 108.0 SFDR for 20 kHz bandwidth with 493.1 μW power consumption.