M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani
{"title":"一个0.18 /spl mu/m 4 Mbit可切换MRAM","authors":"M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani","doi":"10.1109/ICICDT.2004.1309899","DOIUrl":null,"url":null,"abstract":"A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 0.18 /spl mu/m 4 Mbit toggling MRAM\",\"authors\":\"M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani\",\"doi\":\"10.1109/ICICDT.2004.1309899\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309899\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.
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