累加型悬栅MOSFET的分析建模及超低工作功率器件的工艺挑战

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI:10.1109/VTSA.2009.5159315

M. Collonge, M. Vinet, M. Ribeiro, J. Pedini, B. Previtali, T. Ernst, S. Bécu, G. Ghibaudo

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引用次数: 0

摘要

首次提出了累加型悬栅MOSFET的解析模型。对于非常低的功率工作，栅极和栅极氧化物的粘附能需要低至130µJ/m2，以及低于2.3 n /m的双夹紧栅极。实验处理了0.2N/m的悬浮硅纳米线，为器件的缩小尺寸开辟了前景。

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Analytical modeling of Accumulation-Mode Suspended-Gate MOSFET and process challenges for very low operating power devices

For the first time, an analytical model of an Accumulation-Mode Suspended-Gate MOSFET is proposed. For very low power operation, adhesion energies of gate and gate oxide as low as 130µJ/m2 are required as well as sub-2.3N/m doubly clamped gate. Experimentally a 0.2N/m suspended silicon nanowire was processed, opening perspectives for device downscaling.

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2009 International Symposium on VLSI Technology, Systems, and Applications

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