N. Shimizu, Y. Naito, Y. Itoh, Y. Shibata, K. Hashimoto, M. Nishio, A. Asai, K. Ohe, H. Umimoto, Y. Hirofuji
{"title":"一种用于256 Mbit DRAM单元的多缓冲嵌入式LOCOS工艺","authors":"N. Shimizu, Y. Naito, Y. Itoh, Y. Shibata, K. Hashimoto, M. Nishio, A. Asai, K. Ohe, H. Umimoto, Y. Hirofuji","doi":"10.1109/IEDM.1992.307360","DOIUrl":null,"url":null,"abstract":"A new isolation technology, called PBR LOCOS (Poly Buffer Recessed LOCOS) process, has been developed for a 256Mbit DRAM with 0.72 mu m/sup 2/ cell. The features of the PBR LOCOS process are low bird's beak encroachment and defects free isolation, which are achieved by using shallow recess etching, buffer polysilicon, and silicon nitride sidewall. It is formed that the shallow recess etching provides high punch-through voltage of parasitic field transistors. The PBR LOCOS process allows the fabrication of 256Mbit DRAM cells.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells\",\"authors\":\"N. Shimizu, Y. Naito, Y. Itoh, Y. Shibata, K. Hashimoto, M. Nishio, A. Asai, K. Ohe, H. Umimoto, Y. Hirofuji\",\"doi\":\"10.1109/IEDM.1992.307360\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new isolation technology, called PBR LOCOS (Poly Buffer Recessed LOCOS) process, has been developed for a 256Mbit DRAM with 0.72 mu m/sup 2/ cell. The features of the PBR LOCOS process are low bird's beak encroachment and defects free isolation, which are achieved by using shallow recess etching, buffer polysilicon, and silicon nitride sidewall. It is formed that the shallow recess etching provides high punch-through voltage of parasitic field transistors. The PBR LOCOS process allows the fabrication of 256Mbit DRAM cells.<<ETX>>\",\"PeriodicalId\":287098,\"journal\":{\"name\":\"1992 International Technical Digest on Electron Devices Meeting\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 International Technical Digest on Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1992.307360\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307360","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells
A new isolation technology, called PBR LOCOS (Poly Buffer Recessed LOCOS) process, has been developed for a 256Mbit DRAM with 0.72 mu m/sup 2/ cell. The features of the PBR LOCOS process are low bird's beak encroachment and defects free isolation, which are achieved by using shallow recess etching, buffer polysilicon, and silicon nitride sidewall. It is formed that the shallow recess etching provides high punch-through voltage of parasitic field transistors. The PBR LOCOS process allows the fabrication of 256Mbit DRAM cells.<>
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