{"title":"高纵横比~10 TSV通过最后一个从背过程开发和集成","authors":"Xiangy-Yu Wang, Hongyu Li","doi":"10.1109/EPTC.2018.8654305","DOIUrl":null,"url":null,"abstract":"As Moore’s law appears to come to the end when the transistor size approaches to its physical scaling limits, peoples begin to look for the new technology to break through the barrier beyond Moore’s law. TSV is one potential option as it could further increase integration density vertically. In this study, a high aspect ratio 10$\\mu \\mathrm{m} \\times100 \\mu$m TSV from the wafer back side is demonstrated and some of the critical process will be discussed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High Aspect Ratio~10 TSV Via-last-from-back Process Development and Integration\",\"authors\":\"Xiangy-Yu Wang, Hongyu Li\",\"doi\":\"10.1109/EPTC.2018.8654305\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As Moore’s law appears to come to the end when the transistor size approaches to its physical scaling limits, peoples begin to look for the new technology to break through the barrier beyond Moore’s law. TSV is one potential option as it could further increase integration density vertically. In this study, a high aspect ratio 10$\\\\mu \\\\mathrm{m} \\\\times100 \\\\mu$m TSV from the wafer back side is demonstrated and some of the critical process will be discussed.\",\"PeriodicalId\":360239,\"journal\":{\"name\":\"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPTC.2018.8654305\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2018.8654305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Aspect Ratio~10 TSV Via-last-from-back Process Development and Integration
As Moore’s law appears to come to the end when the transistor size approaches to its physical scaling limits, peoples begin to look for the new technology to break through the barrier beyond Moore’s law. TSV is one potential option as it could further increase integration density vertically. In this study, a high aspect ratio 10$\mu \mathrm{m} \times100 \mu$m TSV from the wafer back side is demonstrated and some of the critical process will be discussed.