Rule-based OPC and MPC interaction for implant layers

Implant layers must cover both logic and SRAM devices with good fidelity even if feature density and pitch differ very much. The coverage design rules of implant layers for SRAM and logic to active layer can vary. Lithography targeting could be problematic, since it may cause issues of either over exposure in logic area or under exposure in SRAM area. The rule-based (RB) re-targeting in the SRAM issue features is to compensate the under exposure in SRAM area. However, the global sizing in SRAM may introduce some bridge issues. Selective targeting and communicating with active layer is necessary. Another method is to achieve different mean-to-nominal (MTN) in some special areas during the reticle process. Such implant wafer issues can also be resolved during the lithography and mask optimized data preparing flow or named as lithography tolerance mask process correction (MPC). In this manuscript, this conventional issue will be demonstrated which is either over exposure in logic area or under exposure in bitcell area. The selective rule-based re-targeting concerning active layer will also be discussed, together with the improved wafer CDSEM data. The alternative method is to achieve different mean-to-nominal in different reticle areas which can be realized by lithography tolerance MPC during reticle process. The investigation of alternative methods will be presented, as well as the trade-off between them to improve the wafer uniformity and process margin of implant layers.