针对互连孔软故障检测的窄划线线压缩双嵌套阵列的研制

Proceedings of the 2015 International Conference on Microelectronic Test Structures Pub Date : 2015-03-23 DOI:10.1109/ICMTS.2015.7106112

H. Shinkawata, Nobuo Tsuboi, A. Tsuda, Shingo Sato, Yasuo Yamaguchi

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引用次数: 0

摘要

介绍了一种用于量产阶段的新型可寻址测试结构阵列，即窄划线线压缩双嵌套阵列，称为划线线高灵敏度筛选检测解码测试结构(HSD-S)。在40nm CMOS技术中检测到异常高电阻作为软失效通孔。我们捕获了一个软失效钻头，通过展示超过160倍的高电阻。

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Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via

We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S). Abnormally high resistance as a soft failure via was detected and located in a 40nm CMOS technology. We captured a soft failure bit which had a high resistance via exhibiting over 160 times larger one.

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Proceedings of the 2015 International Conference on Microelectronic Test Structures

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