硅通孔工艺协同优化的整体方法

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI:10.1109/IRPS.2011.5784529

S. Ramaswami

{"title":"硅通孔工艺协同优化的整体方法","authors":"S. Ramaswami","doi":"10.1109/IRPS.2011.5784529","DOIUrl":null,"url":null,"abstract":"As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A holistic approach to process co-optimization for through-silicon via\",\"authors\":\"S. Ramaswami\",\"doi\":\"10.1109/IRPS.2011.5784529\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.\",\"PeriodicalId\":242672,\"journal\":{\"name\":\"2011 International Reliability Physics Symposium\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2011.5784529\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2011.5784529","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

随着硅通孔(TSV)技术从开发到生产的转变，存在着几个共同优化工艺的机会，以确保更宽的工艺窗口，同时满足成本目标和制造稳健性。讨论了涉及蚀刻、CVD、PVD、ECD、CMP和晶圆支持系统(载流子晶圆)的通孔中间、通孔显露和通孔最后集成方案的权衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A holistic approach to process co-optimization for through-silicon via

As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 International Reliability Physics Symposium

自引率

0.00%

发文量