通过设计和工艺优化降低FinFET电阻

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI:10.1109/VTSA.2009.5159323

Cindy Wang, Josephine B. Chang, Chung-Hsun Lin, Arvind Kumar, A. Gehring, Jin Cho, A. Majumdar, A. Bryant, Z. Ren, Kevin K. H. Chan, T. Kanarsky, Xinlin Wang, O. Dokumaci, M. Guillorn, M. Khater, Qingyun Yang, Xi Li, M. Naeem, J. Holt, Y. Moon, J. King, J. Yates, Ying Zhang, Dae-gyu Park, C. Ouyang, W. Haensch

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引用次数: 9

摘要

由于优越的静电性能，在22nm技术节点上，与平面fet相比，本质FinFET器件结构可以提供大约10-20%的延迟减少。然而，由于薄体通道和三维器件结构，finfet更容易产生寄生电阻和电容。在这里，我们提出了最小化FinFET寄生电阻的策略，并讨论了整体器件设计优化。使用45纳米节点尺寸的finfet，我们展示了具有230/350外部电阻Ω-um的finfet / fet。

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FinFET resistance mitigation through design and process optimization

The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.

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2009 International Symposium on VLSI Technology, Systems, and Applications

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