{"title":"带片上EPROM的14-b 2.5 MSPS流水线ADC","authors":"D. Mercer","doi":"10.1109/BIPOL.1994.587844","DOIUrl":null,"url":null,"abstract":"A 14-b 2.5-MSPS, multi-stage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, \"write once\" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as +/- 2LSB, and differential nonlinearity errors of -0.6, +0.8 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5-V reference is built on a 2-/spl mu/m 10-V BiCMOS process and consumes 550 mW of power.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A 14-b 2.5 MSPS pipelined ADC with on chip EPROM\",\"authors\":\"D. Mercer\",\"doi\":\"10.1109/BIPOL.1994.587844\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 14-b 2.5-MSPS, multi-stage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, \\\"write once\\\" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as +/- 2LSB, and differential nonlinearity errors of -0.6, +0.8 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5-V reference is built on a 2-/spl mu/m 10-V BiCMOS process and consumes 550 mW of power.\",\"PeriodicalId\":373721,\"journal\":{\"name\":\"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1994.587844\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1994.587844","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 14-b 2.5-MSPS, multi-stage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, "write once" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as +/- 2LSB, and differential nonlinearity errors of -0.6, +0.8 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5-V reference is built on a 2-/spl mu/m 10-V BiCMOS process and consumes 550 mW of power.