G. Marti, Ankit Pokhrel, G. Murdoch, G. Delie, Anshul Gupta, P. Marien, A. Lesniewska, S. Decoster, Souvik Kundu, Q. Le, Y. Oniki, B. Kenens, Y. Hermans, Seongho Park, Z. Tokei
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Two-level Semi-damascene interconnect with fully self-aligned Vias at MP18
We present the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects varying 26 to 18nm metal pitch, using an EUV-based SADP scheme and subsequent direct etch of Ru, manufactured on 300mm wafers. The integration flow uses the subtractive etching principle of Ru on two subsequent metal levels. Single via resistance landing on 18nm pitch Ru lines shows that > 85% of the devices meet the target of <50Ω. Furthermore, the via chain offers a yield of 60% with a resistance close to the target of ~5k Ω. Besides, we show good uniformity and high VBD via-to-line with MP20 to MP26, establishing FSAV.
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