Spatio-temporal mapping of device temperature due to self-heating in Sub-22 nm transistors

With the increase of transistor density and adoption of novel geometries, such as, FinFET, ETSOI, and gate-all-around nanowire (GAA NW) transistors, self-heating has emerged as a persistent concern for modern ICs. Various reliability issues, such as, NBTI, HCI, PBTI, and TDDB depend sensitively on channel temperature, ΔTc(x, y, z;t), due to self-heating. An accurate spatio-temporal map of channel temperature is essential for Fin/NW-resolved reliability/lifetime of sub-22 nm technology nodes. In this paper, we demonstrate that (i) none of the existing techniques, in isolation, can map the NW-resolved channel temperature of modern transistors, and (ii) only a collection of orthogonal techniques (multiprobe approach) or novel test structures (material approach), integrated/interpreted through self-consistent electro-thermal simulation, can map the temperature in sufficient detail necessary for reliability prediction.