{"title":"多项目晶圆的平面规划","authors":"Meng-Chiou Wu, Shr-Cheng Tsai, Rung-Bin Lin","doi":"10.1109/VDAT.2006.258145","DOIUrl":null,"url":null,"abstract":"Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Floorplanning Multiple Reticles for Multi-project Wafers\",\"authors\":\"Meng-Chiou Wu, Shr-Cheng Tsai, Rung-Bin Lin\",\"doi\":\"10.1109/VDAT.2006.258145\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2006.258145\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Floorplanning Multiple Reticles for Multi-project Wafers
Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers
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