改进电源完整性的第二代集成堆叠电容器(ISC)

Won Ji Park, J. Oh, Shaofeng Ding, Woo Seong Jang, Hyung Won Kim, Young Bin Hyun, Tae Kyun Kim, Seung Ki Nam, Jung Il Son, Seong Wook Moon, Jeonghoon Ahn, J. Ku, Sunoo Kim
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引用次数: 0

摘要

电容器是射频(RF)和混合信号集成电路(ic)等各种电子应用中实现高性能的关键部件之一。本文开发了第二代集成堆叠电容器(ISC GEN-2)作为去耦电容器,并通过仿真、电容(Ci)、漏电流和WLR(晶圆级可靠性)结果对其进行了表征。ISC GEN-2的电容在1000 fF/um2以上,比第一代ISC (ISC GEN-1)高出约3倍。在ISC GEN-2上改进了电容,与LICC (Low Inductance Chip Capacitor)相比,在给定的电路仿真中显示出更低的电压噪声,~0.66x。WLR结果显示达到了预期的要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The Second Generation of Integrated Stack Capacitor (ISC) for Power Integrity Improvement
Capacitors are the one of the key parts in a wide variety of electronic applications, such as radio-frequency (RF) and mixed-signal integrated circuits (ICs), to achieve high performance. In this paper, the 2nd generation of integrated stack capacitor (ISC GEN-2) was developed as a decoupling capacitor and characterized by using a simulation, capacitance (Ci), leakage current and WLR (Wafer Level Reliability) results. The capacitance of ISC GEN-2 is above 1,000 fF/um2 and approximately 3 times higher than the 1st generation of ISC (ISC GEN-1). With an improved capacitance on ISC GEN-2, it showed lower voltage noise, ~0.66x, compared to LICC (Low Inductance Chip Capacitor) at a given circuit simulation. The WLR results showed to meet the desired requirements.
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