智能计算应用中异构集成的扇出MCM解决方案研究

C. Hung, Yu-Po Wang, Steven Chen, Katch Wan
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引用次数: 0

摘要

近年来,半导体产品发展迅速,从具备基本计算能力的台式电脑到可联网的智能手机,再到智能家电、智能手表的量产,以及正在研发中的智能眼镜等新兴智能和感知智能系统产品。产品的发展趋势是向高性能、多功能集成化、更薄的外形和更低的成本发展。这些要求与晶圆技术和组装工艺的发展有关。先进的晶圆技术,如5nm / 3nm,将提供更高的性能。然而,随着摩尔定律接近物理极限,业界已经转向开发先进的封装解决方案技术来突破这一瓶颈。目前,业界具有前瞻性的封装平台包括2.5 D、3D、Fan-out和SiP模块等,这些技术可以集成小片、芯片堆栈、无源元件作为异构集成封装解决方案。扇出MCM平台具有均质/异质晶圆和无源的综合特性,比2.5D具有更低的成本和更低的外形优势,并且通过适当的RDL /衬底布局设计也提供了与2.5D相当的性能。此外,为满足产品的高性能特点,朝着开发多层RDL层(3层以上)方向发展。本文将规划一系列多RDL层样品试验,RDL样品构建线宽/线距为1/1um,并介绍相关工艺挑战、微观结构数据。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fan-Out MCM Solutions Study for Heterogeneous Integration on Intelligent Computing Application
In recent years, semiconductor products have developed rapidly, from desktop computers with basic computing to Internet-connected smartphones, to emerging intelligent and perceived smart system products, such as mass-produced of smart home appliances, smart watches, and under development of smart glasses. The product trend is toward high performance, multi-functional integration, thinner profile and lower cost features. These requirements are interrelated with wafer technology and assembly process development. The advanced wafer technology, such as 5nm / 3nm, will provide higher performance. However, as Moore’s Law is approaching the physical limit, the industry has turned to the development of advanced packaging solution technologies to break through this bottleneck. At present, the industry’s forward-looking packaging platform includes 2.5 D, 3D, Fan-out and SiP modules, etc., which technologies can integrate chiplet, chip stack, passive components as heterogeneous integrated packaging solutions. Fan-Out MCM Platform has integrative characteristics for homogeneous / heterogeneous wafers and passives, lower cost and lower profile advantage than 2.5D, also provided comparable performance to 2.5D by proper RDL / Substrate layout design. In addition, in order to meet the high-performance characteristics of products, toward developing multi-layer RDL layers (more than 3 layers). This article will plan a series of multi-RDL layers sample tests, RDL sample build of line width/line space of 1/1um and introduce the related process challenge, microstructure data.
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