Co-optimization of security and accessibility to on-chip instruments

The semiconductor technology development constantly enables integrated circuits (ICs) with more, faster and smaller transistors. While there are many advantages, there are also many and new challenges, for example tighter margins, wear-outs and process variations. To address these challenges, the traditional approach with external test instruments used at man-ufacturing test must be complemented with on-chip instruments to provide possibilities to test for defects that manifest themselves during the operational lifetime. These on-chip instruments provide, on one hand, better controllability and observability, which is helpful for testing purposes. On the other hand, the increased possibility to control and observable the IC's internals can be a security risk. We discuss how to provide access and how to co-optimize security and accessibility for these on-chip instruments.